Design & Reuse
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992 IP
251
1.0
SMIC 0.18um Mini-LVDS Transmitter
The Mini-LVDS transmitter converts up to 48-bit or 36-bit RGB parallel data into 6-pair/3-pair of Mini-LVDS data stream that can support transmission ...
252
1.0
SMIC 0.18um SSTL2
VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
253
1.0
SMIC 0.18um SSTL3
VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
254
1.0
SMIC 0.18um SSTL_18 I/O
SSTL_18 (Stub Series Terminated Logic for 1.8v) is an electrical interface commonly used with DDR2....
255
1.0
SMIC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library
VeriSilicon SMIC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
256
1.0
SMIC 0.25um 2.5V/3.3V SSTL3 I/O Cell Library
VeriSilicon SMIC 0.25um 2.5V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
257
1.0
SMIC 55nm LP Multiple Power Supply IO library
Multiple power supply IO library for SMIC55nm low power 1.2v/2.5v process...
258
1.0
SMIC 55nm sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....
259
1.0
SMIC 55nm sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....
260
1.0
SMIC13 High Speed process, 1.2/1.5V High Speed Transceiver Logic IO
VeriSilicon SMIC 0.13um 1.2V/1.5V HSTL I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporatio...
261
1.0
SMIC18 General process, Multi-Voltage IO with high voltage voltence
SMIC18 General process, Multi-Voltage IO, driver current: 2mA~16mA when 3.3v IO supply...
262
1.0
SMIC18 General process, Multi-Voltage IO, driver current: 10mA~80mA
SMIC18 General process, Multi-Voltage IO, driver current: 10mA~80mA...
263
1.0
SMIC18 General process, Multi-Voltage IO, High ESD perfermance
SMIC18 General process, Multi-Voltage IO, High ESD perfermance...
264
1.0
Sony Camera LVDS Interface
The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA. It serves as a direct replacement for an exte...
265
1.0
Programmable Special IO in SMIC0.13um
AR750S13 is a programmable special IO cell supporting various JEDEG standards, such as LVDS, LVTTL, LVCMOS-33/25/18/15, SSTL_3/2/18. The IP is extreme...
266
1.0
NSI 0.13um RFSOI Process Multiple power supply IO library
NSI 0.13um RFSOI 1.8V/2.5V Multiple power supply IO Library...
267
1.0
GSMC 0.11um CIS process LVDS Transceiver Pad
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between them can be up to 650Mhz. The LVDS...
268
1.0
GSMC 0.13um IO Library
GSMC 0.13um process 1.2v/3.3v Generic IO library...
269
1.0
CSMC 0.13um IO Library
CSMC 0.13um process 1.2v/3.3v Generic IO library...
270
1.0
GSMC 0.13um LP IO Library
GSMC 0.13um LP process 1.2v/3.3v Generic IO library...
271
1.0
CSMC 0.13um LP IO Library
CSMC 0.13um LP process 1.2v/3.3v Generic IO library...
272
1.0
GSMC 0.14um LV IO Library
GSMC 0.14um LV process 1.2v/3.3v Generic IO library...
273
1.0
GSMC 0.15um IO Library
GSMC 0.15um process 1.5v/3.3v Generic IO library...
274
1.0
GSMC 0.15um LP IO Library
GSMC 0.15um LP process 1.5v/3.3v Generic IO library...
275
1.0
GSMC 0.15um LV IO Library
GSMC 0.15um LV process 1.5v/3.3v Generic IO library...
276
1.0
GSMC 0.15um ULP IO Library
GSMC 0.15um ULP process 1.8v/2.8v Generic IO library...
277
1.0
GSMC 0.16um IO Library
GSMC 0.16um process 1.8v/3.3v Generic IO library...
278
1.0
CSMC 0.16um IO Library
CSMC 0.16um process 1.8v/3.3v Generic IO library...
279
1.0
GSMC 0.18um 1.8V/3.3V DUP I/O Library
VeriSilicon GSMC 0.18um 1.8V/3.3V DUP I/O Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18u...
280
1.0
GSMC 0.18um 1.8V/3.3V Multiple I/O
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (02) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing (GSMC) 0....
281
1.0
GSMC 0.18um 1.8V/3.3V Multiple I/O
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (03) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporati...
282
1.0
GSMC 0.18um CIS process LVDS Transceiver Pad
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between them can be up to 650Mhz. The LVDS...
283
1.0
GSMC 0.18um cost effective IO Library
GSMC 0.18um G9 process 3.3v/3.3v Generic IO library...
284
1.0
GSMC 0.18um cost effective IO Library
GSMC 0.18um G9 process 3.3v/5v Generic IO library...
285
1.0
GSMC 0.18um Crystal Oscillator IO
This is a crystal oscillator IO pad designed for low-power consumption application. The OSC power supply is 3.3V, and the IO pad provides clock signal...
286
1.0
GSMC 0.18um IO Library
GSMC 0.18um process 1.8v/3.3v Generic IO library...
287
1.0
CSMC 0.18um IO Library
CSMC 0.18um process 1.8v/3.3v Generic IO library...
288
1.0
GSMC 0.18um LP IO Library
GSMC 0.18um LP process 1.8v/3.3v Generic IO library...
289
1.0
GSMC 0.18um ULL IO Library
GSMC 0.18um ULL process 1.8v/3.3v Generic IO library...
290
1.0
GSMC 0.25um IO Library
GSMC 0.25um process 2.5v/3.3v Generic IO library...
291
1.0
CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.
VeriSilicon CSMC 0.13μm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Central Semiconductor Manufacturing Corporation (CSMC...
292
1.0
GSMC16RF process VPPIO, provides 6.5V power supply IO pads for OTP application.
VeriSilicon GSMC 0.16um RF 1.8V/3.3V VPPIO_DUP_01 IO library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (...
293
1.0
ST28nm LVDS Transmitter
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...
294
1.0
Huali 28nm HKCP process Multiple Power Supply IO library
The Multiple I/O Library supports both 2.5V analog IO cells & 3.3V digital IO cells. Digital IO contains 5V tolerance, open-drain & OSC cells. This li...
295
1.0
LVDS
This IP is a high-speed LVDS (Low-Voltage Differential Signaling) transceiver supporting multi-channel joint. The LVDS TX & RX IP is specified for ope...
296
1.0
LVDS RX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
297
1.0
LVDS TX
...
298
1.0
LVDS TX Combo TTL PHY
Innosilicon LVDS implements LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains four 7-bit parallel-load serial-out shift registers, a 7X clock...
299
1.0
LVDS TX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
300
0.3729
1.2V Temperarure sensor (0.5 degree C accuracy) - TSMC 5nm 5FF
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...